所谓 发明自己的CPU 我想应该是这样:1.自己老老实实自己用VHDL或VERILOG写
ip core (其实ip core几十个VHD或V文件)
2.用综合器一步步综合成自己的标准单元电路
3.布线制版
一。龙芯的ip core由来
首先看一段代码(设置好福珑上的编程环境).data
mess: .asciiz “\n hello world ”
.globl main
.text
main:
li $v0, 4 # 打印的系统中断号
la $a0, mess# 要打印的字符串的地址
syscall # 调中断
.end main 这是在福珑机子(基于龙芯2E)上简单的一段HELLO WORLD汇编代码,可以看出所有指令(li la 还有这个程序没有包含的龙芯指令都和MIPS指令完全一样)都是MIPS指令,代码段和数据段和系统调用的约定都是MIPS指令集约定,为进一步确定龙芯指令集就是MIPS指令集,我查看连接后的二进制代码,再和MIPS手册指令的opcode对比,结果完全一样。连指令的名称到OPCODE都一样,我真是无语了。cpu的各模块 ROM<-------| |----->decode单元
-----央控制单元-----
RAM<-------| |----->ALU单元1。中央处理单元从ROM(指令寄存器与内存统一编址)取指令
2。然后通过decode单元译码(指令--->opcode)
3。ALU单元执行decode单元译出来的码(opcode)
4. 访RAM取数据等操作数
5。回写我们都知道CPU的IP CORE基本都是由VHDL或VERILOG写成,而其中必然有一decode模块将指令转化为OPCODE,例如8051的ip core的i8051_dec.vhd文件中的decode模块:
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
--decode单元
--i8051_dec.vhd文件entity I8051_DEC is
port(rst : in STD_LOGIC;
op_in : in UNSIGNED (7 downto 0);
op_out : out UNSIGNED (8 downto 0));
end I8051_DEC;architecture DFL of I8051_DEC is
begin
op_out <= ("00" & OPC_ERROR ) when rst = '1'else
--call译码 ("01" & OPC_ACALL ) when op_in(4 downto 0) = ACALL else
--加法译码 等 ("00" & OPC_ADD_1 ) when op_in(7 downto 3) = ADD_1 else
("01" & OPC_ADD_2 ) when op_in(7 downto 0) = ADD_2 else
("00" & OPC_ADD_3 ) when op_in(7 downto 1) = ADD_3 else
("01" & OPC_ADD_4 ) when op_in(7 downto 0) = ADD_4 else
("00" & OPC_ADDC_1) when op_in(7 downto 3) = ADDC_1 else
("01" & OPC_ADDC_2) when op_in(7 downto 0) = ADDC_2 else
("00" & OPC_ADDC_3) when op_in(7 downto 1) = ADDC_3 else
("01" & OPC_ADDC_4) when op_in(7 downto 0) = ADDC_4 else
("01" & OPC_AJMP ) when op_in(4 downto 0) = AJMP else
.
.
.
.
("00" & OPC_ERROR );
end DFL;不难推断龙芯CPU的ip core中肯定存在类似文件(也许叫loognxin_dec.vhd,或者其实就是MIPS_dec.vhd)包含decode模块,形式和这个近似。
////////////////////////////////////////////////////////////////////////////////////////////////////////
--央控制单元
--i8051_ctr.vhd
architecture BHV of I8051_CTR is type CPU_STATE_TYPE is (CS_0, CS_1, CS_2, CS_3);
type EXE_STATE_TYPE is (ES_0, ES_1, ES_2, ES_3, ES_4, ES_5, ES_6, ES_7);
signal reg_pc_15_11 : UNSIGNED (4 downto 0);
signal reg_pc_10_8 : UNSIGNED (2 downto 0);
signal reg_pc_7_0 : UNSIGNED (7 downto 0);
signal reg_op1 : UNSIGNED (7 downto 0);
signal reg_op2 : UNSIGNED (7 downto 0);
signal reg_op3 : UNSIGNED (7 downto 0);
signal reg_acc : UNSIGNED (7 downto 0);
signal reg_cy : STD_LOGIC;
signal reg_ac : STD_LOGIC;
signal reg_f0 : STD_LOGIC;
signal reg_rs1 : STD_LOGIC;
signal reg_rs0 : STD_LOGIC;
signal reg_ov : STD_LOGIC;
signal reg_nu : STD_LOGIC;
signal reg_p : STD_LOGIC; signal cpu_state : CPU_STATE_TYPE;
signal exe_state : EXE_STATE_TYPE;
begin process(rst, clk) -- execute state
--
when CS_3 =>
case dec_op_in(6 downto 0) is-------------------------------------------------------------------------------
--
-- acc <- acc + (r)
--
when OPC_ADD_1 => --注意这一行 表示加法
case exe_state is
when ES_0 =>
GET_RAM_ADDR_1(v8);
START_RD_RAM(v8);
exe_state <= ES_1; when ES_1 =>
exe_state <= ES_2; when ES_2 =>
alu_op_code <= ALU_OPC_ADD;
alu_src_1 <= reg_acc;
alu_src_2 <= ram_in_data;
alu_src_cy <= '0';
exe_state <= ES_3; when ES_3 =>
ram_out_data <= alu_des_1;
START_WR_RAM(R_ACC);
reg_cy <= alu_des_cy;
reg_ac <= alu_des_ac;
reg_ov <= alu_des_ov;
exe_state <= ES_4; when OPC_CJNE_3 => --注意这一行表示不等跳转http://www.shenyangfp8.comhttp://www.quanzhoufp.com
下面还有许多不一一列 case exe_state is
when ES_0 =>
GET_RAM_ADDR_1(v8);
START_RD_RAM(v8);
exe_state <= ES_1; when ES_1 =>
exe_state <= ES_2; when ES_2 =>
GET_PC_H(pch);
GET_PC_L(pcl);
alu_op_code <= ALU_OPC_PCSADD;
alu_src_1 <= pcl;
alu_src_2 <= pch;
if( ram_in_data /= reg_op2 ) then
ip core (其实ip core几十个VHD或V文件)
2.用综合器一步步综合成自己的标准单元电路
3.布线制版
一。龙芯的ip core由来
首先看一段代码(设置好福珑上的编程环境).data
mess: .asciiz “\n hello world ”
.globl main
.text
main:
li $v0, 4 # 打印的系统中断号
la $a0, mess# 要打印的字符串的地址
syscall # 调中断
.end main 这是在福珑机子(基于龙芯2E)上简单的一段HELLO WORLD汇编代码,可以看出所有指令(li la 还有这个程序没有包含的龙芯指令都和MIPS指令完全一样)都是MIPS指令,代码段和数据段和系统调用的约定都是MIPS指令集约定,为进一步确定龙芯指令集就是MIPS指令集,我查看连接后的二进制代码,再和MIPS手册指令的opcode对比,结果完全一样。连指令的名称到OPCODE都一样,我真是无语了。cpu的各模块 ROM<-------| |----->decode单元
-----央控制单元-----
RAM<-------| |----->ALU单元1。中央处理单元从ROM(指令寄存器与内存统一编址)取指令
2。然后通过decode单元译码(指令--->opcode)
3。ALU单元执行decode单元译出来的码(opcode)
4. 访RAM取数据等操作数
5。回写我们都知道CPU的IP CORE基本都是由VHDL或VERILOG写成,而其中必然有一decode模块将指令转化为OPCODE,例如8051的ip core的i8051_dec.vhd文件中的decode模块:
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
--decode单元
--i8051_dec.vhd文件entity I8051_DEC is
port(rst : in STD_LOGIC;
op_in : in UNSIGNED (7 downto 0);
op_out : out UNSIGNED (8 downto 0));
end I8051_DEC;architecture DFL of I8051_DEC is
begin
op_out <= ("00" & OPC_ERROR ) when rst = '1'else
--call译码 ("01" & OPC_ACALL ) when op_in(4 downto 0) = ACALL else
--加法译码 等 ("00" & OPC_ADD_1 ) when op_in(7 downto 3) = ADD_1 else
("01" & OPC_ADD_2 ) when op_in(7 downto 0) = ADD_2 else
("00" & OPC_ADD_3 ) when op_in(7 downto 1) = ADD_3 else
("01" & OPC_ADD_4 ) when op_in(7 downto 0) = ADD_4 else
("00" & OPC_ADDC_1) when op_in(7 downto 3) = ADDC_1 else
("01" & OPC_ADDC_2) when op_in(7 downto 0) = ADDC_2 else
("00" & OPC_ADDC_3) when op_in(7 downto 1) = ADDC_3 else
("01" & OPC_ADDC_4) when op_in(7 downto 0) = ADDC_4 else
("01" & OPC_AJMP ) when op_in(4 downto 0) = AJMP else
.
.
.
.
("00" & OPC_ERROR );
end DFL;不难推断龙芯CPU的ip core中肯定存在类似文件(也许叫loognxin_dec.vhd,或者其实就是MIPS_dec.vhd)包含decode模块,形式和这个近似。
////////////////////////////////////////////////////////////////////////////////////////////////////////
--央控制单元
--i8051_ctr.vhd
architecture BHV of I8051_CTR is type CPU_STATE_TYPE is (CS_0, CS_1, CS_2, CS_3);
type EXE_STATE_TYPE is (ES_0, ES_1, ES_2, ES_3, ES_4, ES_5, ES_6, ES_7);
signal reg_pc_15_11 : UNSIGNED (4 downto 0);
signal reg_pc_10_8 : UNSIGNED (2 downto 0);
signal reg_pc_7_0 : UNSIGNED (7 downto 0);
signal reg_op1 : UNSIGNED (7 downto 0);
signal reg_op2 : UNSIGNED (7 downto 0);
signal reg_op3 : UNSIGNED (7 downto 0);
signal reg_acc : UNSIGNED (7 downto 0);
signal reg_cy : STD_LOGIC;
signal reg_ac : STD_LOGIC;
signal reg_f0 : STD_LOGIC;
signal reg_rs1 : STD_LOGIC;
signal reg_rs0 : STD_LOGIC;
signal reg_ov : STD_LOGIC;
signal reg_nu : STD_LOGIC;
signal reg_p : STD_LOGIC; signal cpu_state : CPU_STATE_TYPE;
signal exe_state : EXE_STATE_TYPE;
begin process(rst, clk) -- execute state
--
when CS_3 =>
case dec_op_in(6 downto 0) is-------------------------------------------------------------------------------
--
-- acc <- acc + (r)
--
when OPC_ADD_1 => --注意这一行 表示加法
case exe_state is
when ES_0 =>
GET_RAM_ADDR_1(v8);
START_RD_RAM(v8);
exe_state <= ES_1; when ES_1 =>
exe_state <= ES_2; when ES_2 =>
alu_op_code <= ALU_OPC_ADD;
alu_src_1 <= reg_acc;
alu_src_2 <= ram_in_data;
alu_src_cy <= '0';
exe_state <= ES_3; when ES_3 =>
ram_out_data <= alu_des_1;
START_WR_RAM(R_ACC);
reg_cy <= alu_des_cy;
reg_ac <= alu_des_ac;
reg_ov <= alu_des_ov;
exe_state <= ES_4; when OPC_CJNE_3 => --注意这一行表示不等跳转http://www.shenyangfp8.comhttp://www.quanzhoufp.com
下面还有许多不一一列 case exe_state is
when ES_0 =>
GET_RAM_ADDR_1(v8);
START_RD_RAM(v8);
exe_state <= ES_1; when ES_1 =>
exe_state <= ES_2; when ES_2 =>
GET_PC_H(pch);
GET_PC_L(pcl);
alu_op_code <= ALU_OPC_PCSADD;
alu_src_1 <= pcl;
alu_src_2 <= pch;
if( ram_in_data /= reg_op2 ) then
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