Assumption:
An input buffered crossbar switch consists of 8 input ports and 8 output ports. Each input port contains a FIFO for the incoming packets. There is a packet generator in each input port that generates packets with Bernoulli trials. When a packet is generated the destination output port and birth time is stamped. In one clock cycle an incoming packet can go into the FIFO and travel through the crossbar if there is no contention. Otherwise the packet has to wait in the FIFO and wait for the arbitration success from the output port. There is one arbiter in each output port that randomly grants different input ports. A packet destroyer residing in each output port kills the packets and collects the packet latency data by comparing the packet birth time and the system clock.Assignment:
Please write a C++ program to simulate this system, with uniformly distributed traffic. Draw a graph of latency VS injection rate (from 1%, 2%...to 100%) with the simulation length of 10000 clock cycles for each injection rate.Requirement:
The code should be able to be compiled with VC++2008. Each input port and output port should be implemented as a class. For an input port it should contain at least a packet generating function, a FIFO structure. An output port should contain at least an arbiter function and a packet destroyer/data collector. Finally there should be a packet class.
An input buffered crossbar switch consists of 8 input ports and 8 output ports. Each input port contains a FIFO for the incoming packets. There is a packet generator in each input port that generates packets with Bernoulli trials. When a packet is generated the destination output port and birth time is stamped. In one clock cycle an incoming packet can go into the FIFO and travel through the crossbar if there is no contention. Otherwise the packet has to wait in the FIFO and wait for the arbitration success from the output port. There is one arbiter in each output port that randomly grants different input ports. A packet destroyer residing in each output port kills the packets and collects the packet latency data by comparing the packet birth time and the system clock.Assignment:
Please write a C++ program to simulate this system, with uniformly distributed traffic. Draw a graph of latency VS injection rate (from 1%, 2%...to 100%) with the simulation length of 10000 clock cycles for each injection rate.Requirement:
The code should be able to be compiled with VC++2008. Each input port and output port should be implemented as a class. For an input port it should contain at least a packet generating function, a FIFO structure. An output port should contain at least an arbiter function and a packet destroyer/data collector. Finally there should be a packet class.
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